๐ Combinational vs Sequential Circuits
Understanding the difference between combinational and sequential circuits is foundational to designing reliable, audit-ready hardware systems. This note breaks down both styles with annotated clarity.
๐ Combinational Circuits
Definition: Circuits whose outputs depend only on current inputsโno memory, no timing.
assign y = a & b;Behavior
- Output updates instantly when inputs change.
- No concept of time or history.
โ Characteristics
- Stateless: no internal memory.
- Timing-independent: output changes as soon as inputs do.
- Used for: logic gates, multiplexers, decoders, ALUs.
๐ Notes
- Can be written using
assignoralways @(*). - Ideal for pure logic transformations.
- Cannot model behavior that depends on past inputs.
โฑ๏ธ Sequential Circuits
Definition: Circuits whose outputs depend on current inputs and past statesโthey store values across time.
reg [3:0] counter;
always @(posedge clk) begin
counter <= counter + 1;
endBehavior
- Output updates only on clock edge or triggering event
- Stores internal state using flip-flops or latches
โ Characteristics
- Stateful: remembers past values.
- Timing-dependent: reacts to clock or control signals.
- Used for: FSMs, counters, registers, pipelines.
๐ Notes
- Requires
regand clockedalwaysblocks. - Enables modeling of time-aware systems.
- Essential for control flow, synchronization, and data retention.
๐งช Comparison Table
| Feature | Combinational Circuit | Sequential Circuit |
|---|---|---|
| Depends on | Current inputs only | Inputs + stored state |
| Timing | Instantaneous | Clocked or event-driven |
| Memory | โ None | โ Flip-flops, latches |
| Syntax | assign, always @(*) | always @(posedge clk) |
| Use case | Logic gates, ALUs | FSMs, counters, registers |
| State retention | โ No | โ Yes |
๐งญ When to Use Each
Use combinational circuits when:
- You need pure logic transformations.
- Output should reflect inputs immediately.
- No history or timing is involved.
Use sequential circuits when:
- You need to store or remember values.
- Behavior depends on clock cycles or control signals.
- You’re building FSMs, counters, or pipelines.
๐งฐ Vault Notes
Rule of Thumb
If your circuit needs memory or timing, it’s sequential.
If itโs just logic transformation, itโs combinational.
โน๏ธ
Combinational Decoder
reg [3:0] out;
always @(*) begin
case (in)
2'b00: out = 4'b0001;
2'b01: out = 4'b0010;
2'b10: out = 4'b0100;
2'b11: out = 4'b1000;
endcase
endโน๏ธ
Sequential Counter
reg [3:0] count;
always @(posedge clk) begin
if (rst)
count <= 0;
else
count <= count + 1;
endโ ๏ธ
Common Mistake
Donโt use combinational logic to model behavior that depends on time or historyโit will fail in synthesis or simulation.
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