๐งท Latches
A latch is a bistable circuit that stores one bit of data. It is level-sensitive, meaning its output can change as long as the control signal (often called “enable”) is active.
โ๏ธ Key Characteristics
- ๐งฎ Memory: Stores a binary state (
0or1) - ๐ Level-sensitive: Responds continuously while enabled
- โฑ๏ธ Asynchronous: Can change state without a clock edge
๐ค Common Types
| ๐ง Type | ๐ข Inputs | ๐ Behavior |
|---|---|---|
| SR Latch | Set, Reset | Sets or resets output |
| Gated SR | Set, Reset, Enable | Adds control gating |
| D Latch | Data, Enable | Captures input when enabled |
๐งฎ SR Latch Logic (NOR-based)
- โ Set = 1, Reset = 0 โ Output = 1
- โ Set = 0, Reset = 1 โ Output = 0
- ๐ Set = 0, Reset = 0 โ Holds previous state
- โ ๏ธ Set = 1, Reset = 1 โ Invalid (undefined)
๐งฐ Use Cases
- ๐๏ธ Temporary storage
- ๐ Debouncing switches
- ๐งฑ Building blocks for flip-flops
๐ช Visual Analogy
Imagine a door that opens only when the “enable” signal is held. While open, the latch listens and updates. When closed, it holds its last state.
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