🔁 `always` and `end`

Understanding the role of always and end in Verilog is essential for modeling reactive logic and building audit-ready hardware systems. This note scaffolds their purpose, behavior, and relationship to control flow.

🔁 always Block

Definition: A procedural block that executes when triggered by a sensitivity list.

always @(*) begin
    y = a & b;
end

✅ Characteristics

• Event-driven: triggered by changes or clock edges.
• Encapsulates logic: can include if, case, loops, assignments.
• Used for: FSMs, counters, decoders, ALUs.

📌 Notes

• always @(*) → combinational logic
• always @(posedge clk) → sequential logic
• Not a decision—it’s a scope for reactive behavior

🔚 end Keyword

Definition: Closes a begin block or control structure.

always @(*) begin
    if (sel)
        y = a;
    else
        y = b;
end

✅ Characteristics

• Structural: defines block boundaries.
• Required when using begin for multiple statements.
• Optional for single-line control flow.

🧪 Comparison Table

🧭 Is always Like if-else?

✅ Clarification

• You write if-else inside an always block.
• The always block itself is not a decision, it’s a triggered container.

🧪 Example

always @(*) begin
    if (sel)
        y = a;
    else
        y = b;
end

• This models a multiplexer.
• The block runs whenever sel, a, or b changes.
• The if-else is the decision logic; always is the reactive wrapper.

🧰 Vault Notes

always @(*) begin
    case (in)
        2'b00: out = 4'b0001;
        2'b01: out = 4'b0010;
        2'b10: out = 4'b0100;
        2'b11: out = 4'b1000;
    endcase
end

always @(posedge clk) begin
    if (rst)
        count <= 0;
    else
        count <= count + 1;
end